For semiconductor apparatuses such as CMOS image sensors having a structure where a plurality of sensors are arranged in array form, there have been increased demands for highly-developed signal processing and miniaturization.
In order to realize this, Patent Document 1, for example, has proposed a method of laminating chips together to integrate a larger signal processing circuit having the same chip size as before.
Such a semiconductor apparatus has a laminated structure of a chip (hereinafter referred to as an analog chip) where a sensor array for generating analog signals is mounted and a chip (hereinafter referred to as a digital chip) where a logic circuit for signal processing is mounted.
Then, the semiconductor apparatus connects these chips together through TC(S)Vs (Through Contact (Silicon) VIAs) formed in the analog chip so as to be laminated one on the other, thereby realizing miniaturization.
A challenge for the miniaturization with such a method is to divide circuit blocks related to signal paths for flowing data output from the sensor array into the upper and lower chips.
For example, in an image sensor, the above system uses several thousand or more wirings for fetching signals from the sensor array so as to correspond to the number of pixels arranged in a vertical or horizontal direction.
For this reason, it is necessary to concentrate the TCVs so as to be placed into the paths. Accordingly, a change in the signal of one of the TCVs adjacent to the other of the TCVs with a large amplitude interferes with the signal of the target TCV and causes an error in the signal.
As countermeasures for this interference, the signals transmitted through the TCVs are limited to those (using one or more binary signal lines) quantized in a voltage direction in the related art.
Hereinafter, the countermeasures will be described in detail.
Hereinafter, as the first countermeasures, a description will be given of a case where the signals transmitted through the TCVs are time-discretized and quantized signals, i.e., digital signals. Then, as the second countermeasures, a description will be given of a case where the signals transmitted through the TCVs are continuous-time and quantized signals.
First, a description will be given of the countermeasures where the signals transmitted through the TCVs are time-discretized and quantized signals, i.e., digital signals.
FIG. 1 is a diagram showing a first configuration example where the signals transmitted through the TCVs are time-discretized and quantized signals in a semiconductor apparatus using laminated chips.
A semiconductor apparatus 1 has a laminated structure of an analog chip 2 and a digital chip 3. Among the laminated chips, the analog chip 2 of the semiconductor apparatus 1 manufactured according to an analog process has a plurality of sensors 4 (−0, −1, . . . ) arranged in array form.
The outputs of the sensors 4 are connected to sampling switches 6 (−0, −1, . . . ) for time-discretizing signals through amplifiers 5 (−0, −1, . . . ).
Here, if the power of the signals output from the sensors 4 is substantially large, the outputs of the sensors 4 may be directly connected to the sampling switches without passing through the amplifiers.
The signals time-discretized by the sampling switches 6 are quantized in a voltage direction using quantizers 7 (−0, −1, . . . ).
The quantizers 7 are composed of a plurality of comparators, and each of the comparators compares a certain signal level with an input signal level to quantize the signal.
Here, the quantizers 7 do not have to complete the quantization at a time but may be circuits configured to perform a plurality of stages.
The signals digitized in such a process are transmitted to the digital chip 3 through TCVs 8 (−0, −1, . . . ) and then processed by a digital signal processing circuit 9.
In this case, the signals transmitted through the TCVs 8 are binary signals of a power supply level or a ground (GND) level, and no error is caused in the signals unless the signals are reduced in size to about the half of a power supply voltage. Further, even if the parasitic capacitances of the TCVs 8 cause a delay in the signals, no problem occurs within the setup margin of the signal processing circuit 9.
Next, a description will be given of another configuration example where the signals transmitted through the TCVs are digital signals.
FIG. 2 is a diagram showing a second configuration example where the signals transmitted through the TCVs are time-discretized and quantized signals in a semiconductor apparatus using laminated chips.
In this case, in a semiconductor apparatus 1A, the output signals of sensors 4 are not directly time-discretized by the sampling switches 6 but are time-discretized by SH (sample hold) circuits 10 (−0, −1, . . . ) provided near the sensors 4.
The SH circuits 10 can be realized by only switches and capacitances in the simplest way.
Next, a description will be given of a case where the configuration example shown in FIG. 2 where the signals transmitted through the TCVs are digital signals is applied to an image sensor.
FIG. 3 is a diagram showing a third configuration example where the signals transmitted through the TCVs are time-discretized and quantized signals in a semiconductor apparatus using laminated chips and is a diagram showing an example where the configuration example shown in FIG. 2 is applied to a CMOS image sensor.
Note that in FIG. 3, the same constituents as those of FIGS. 1 and 2 are denoted by the same symbols to facilitate the understanding of the third configuration example.
Mainstream CMOS image sensors have a FD (Floating Diffusion) amplifier for every pixel and are of a column-parallel output type that selects certain rows in a pixel array and simultaneously reads them in a column direction.
This is because parallel processing is advantageous due to the fact that the FD amplifiers arranged in the pixels hardly provide satisfactory driving performance and thus a data rate has to be reduced.
Such a CMOS image sensor 20 is configured to include a pixel array part 21 serving as a sensor array and a row selection circuit (V scanner) 22 that drives pixels.
The pixel array part 21 has pixel circuits 30 arranged in M (rows)×N (columns) matrix form.
The row selection circuit 22 controls the operations of the pixels arranged in any rows of the pixel array part 21. The row selection circuit 22 controls the pixels through control lines LSEL, LRST, and LTRG.
As an example, FIG. 3 shows a case where each of the pixel circuits 30 includes four transistors.
The pixel circuit 30 has a photoelectric conversion element (hereinafter simply referred to as a PD when necessary) 31 composed of, for example, a photodiode (PD). With respect to the one photoelectric conversion element 31, the pixel circuit 30 has four transistors serving as active elements, i.e., a transfer transistor 32, a reset transistor 33, an amplification transistor 34, and a selection transistor 35.
In the CMOS image sensor 20, FDs (Floating Diffusions) (capacitances) and the transfer transistors (transfer switches) 32 realize the function of the sample hold circuits shown in the block diagram of FIG. 2 with respect to the photoelectric conversion elements (photodiodes) 31 serving as sensors.
Second, a description will be given of a case where the signals transmitted through the TCVs are continuous-time and quantized signals.
FIG. 4 is a diagram showing a first configuration example where the signals transmitted through the TCVs are continuous-time and quantized signals in a semiconductor apparatus using laminated chips.
As in the case of the semiconductor apparatus 1A shown in FIG. 2, a semiconductor apparatus 1C shown in FIG. 4 causes comparators 23 (−0, −1, . . . ) to compare signals discretized by the SH circuit 10 with ramp waves generated by a ramp signal generator (not shown), thereby converting analog signals output from the sensors 4 into time-axis signals.
The semiconductor apparatus 1C transmits the quantized sensor signals thus converted to the digital chip 2C through the TCVs 8 and quantizes the time-axis information with counters (TDCs: Time to Digital Converters) 24, thereby obtaining digital signals.
FIG. 5 is a diagram where the above operations are shown using waveforms in a time axis.
When the comparison results of the analog signals and ramp waves RAMP are output from the comparators 23 as signals S23, the counters 24 stop their counting operations and the signals are determined. Here, a timing for starting the ramp waves RAMP and a timing for starting the counting operations with the counters 24 are synchronized with each other. With this operation, voltage information is converted into time information.
When such a transmitting method is used, the signals transmitted through the TCVs 8 are quantized to a power supply level or a ground (GND) level as in a case where digital signals are transmitted.
FIG. 6 is a diagram showing an example where the configuration shown in FIG. 4 is applied to a CMOS image sensor in a semiconductor apparatus using laminated chips.
Note that in FIG. 6, the same constituents as those of FIGS. 3 and 4 are denoted by the same symbols to facilitate the understanding of the semiconductor apparatus.
As in the case of FIG. 4, the semiconductor apparatus causes the comparators 23 (−0, −1, . . . ) to perform the comparison of ramp waves generated by a ramp signal generator 25, thereby converting analog signals output from pixels 30 into time-axis signals.
The semiconductor apparatus transmits the quantized sensor signals thus converted to a digital chip 3D through the TCVs 8, quantizes the time-axis information with the counters (TDCs) 24, and stores obtained digital signals in latches (memories) 26.
The digital signals stored in the latches 26 are horizontally transferred through transfer lines by the signal processing circuit 9.
Note that the comparators 23, the counters 24, and the latches 26 arranged in respective columns form a so-called single slope AD converter (ADC).
FIG. 7 is a diagram showing the configuration of a general single slope AD converter.
A single slope AD converter 40 shown in FIG. 7 is configured to include a comparator 41, a counter 42, and a ramp signal generator 43.
As described above, in the single slope AD converter 40, the comparator 41 compares ramp waves (slope signal) generated by the ramp signal generator 43 such as a DAC with an input signal IN input to the AD converter 40 to control the subsequent-stage counter 42, thereby performing AD conversion.
As a significant performance index of the AD converter 40, noise characteristics are known. The noise characteristics of the comparator 41 often dominate the noise characteristics of the AD converter 40. Examples of noise include thermal noise serving as wide-band noise, flicker noise serving as low-frequency noise, RTS (Random-Telegraph-Signal) noise, or the like, each of which degrades the noise characteristics.
As the methods of reducing such noise, an increase in the sizes of transistors and the arrangement of mirror capacitances at the first-stage outputs of comparators (see Patent Document 2) have been generally known.